The present invention relates to a non-volatile semiconductor memory device, and more particularly, it relates to an electrically erasable and programmable read only memory (EEPROM).
A flash EEPROM (flash memory) including a plurality of non-volatile memory cells each having a control gate, a floating gate, a drain and a source is conventionally known, in which data stored in each predetermined block can be erased in a batch manner.
FIG. 1 shows a distribution of the threshold voltage Vth of memory cells included in the conventional flash memory. In an erase cycle, electrons stored in the floating gate of each memory cell are released, and as a result, each memory cell has a low threshold voltage. The state of the memory cell thus holding a data "0" is herein designated as an erase state or a 0 (zero) state. In a program cycle, electrons are stored in the floating gate of a selected memory cell alone by using mechanism of hot electron injection. The memory cell storing the electrons in its floating gate has a high threshold voltage. The state of the memory cell thus holding a data "1" is herein designated as a program state or a 1 (one) state. In a read cycle, with a positive low potential applied to the drain and a ground potential applied to the source of a memory cell to be read, a predetermined read voltage Vgs is applied between the control gate and the source of the memory cell. When the maximum value of the read voltage, namely, the maximum read voltage, is indicated as Vgsmax, a program operation of the conventional flash memory is conducted over a sufficient time period until all the memory cells to be transit from the 0 state to the 1 state attain a threshold voltage higher than the voltage Vgsmax.
On the other hand, a differential sensing type flash memory with rapid read performance is known. This flash memory includes, in order to read stored data from one memory cell whose state is set in accordance with FIG. 1, one dummy cell having the same configuration as the memory cell and always set to the 0 state, and one differential sense amplifier. The drain of the memory cell is connected to the differential sense amplifier through a first bit line, and the drain of the dummy cell is connected to the differential sense amplifier through a second bit line. The first and second bit lines are set to a predetermined precharge potential VPC at the initial stage of a read cycle.
In the case where the memory cell is in the 0 state, when the read voltage Vgs is applied between the control gate and the source, a drain current is drained from the first bit line, so as to lower the potential of the first bit line. In the case where the memory cell is in the 1 state, even when the read voltage Vgs is applied between the control gate and the source, the memory cell never draws a drain current from the first bit line, and hence, the potential of the first bit line is kept at the precharge potential VPC. On the other hand, when the read voltage Vgs is applied between the control gate and the source of the dummy cell, a drain current is drained from the second bit line, so as to lower the potential of the second bit line. The channel width and/or channel length of the dummy cell is, however, adjusted so that the drain current of the dummy cell can be a half of the drain current of the memory cell set to the 0 state. Accordingly, a reference potential Vref generated by the dummy cell on the second bit line is higher than the potential of the first bit line attained when the memory cell is in the 0 state and is lower than the potential VPC of the first bit line attained when the memory cell is in the 1 state. The differential sense amplifier compares the potentials of the first and second bit lines, thereby accurately sensing the state of the memory cell.
In the conventional flash memory, a program operation is not completed until all the memory cells to be transit from the 0 state to the 1 state attain a threshold voltage higher than the maximum read voltage Vgsmax in order to accurately read a data "1" stored in the memory cell. Accordingly, it takes a disadvantageously long period of time to conduct a program operation (as shown in FIG. 1) .
FIG. 2 shows a problem occurring in a read cycle of the conventional differential sensing type flash memory. Specifically, the problem is that when the read voltage Vgs is unexpectedly increased as a result of increase of a supply voltage, a data "1" stored in a memory cell cannot be accurately read. As shown with a broken line in FIG. 2, the potential of a bit line connected to a memory cell set to the 1 state to have a threshold voltage higher than the read voltage is kept at the potential VPC in a read cycle. When the read voltage Vgs is higher than the threshold voltage Vth of the memory cell in the 1 state, namely, when Vgs&gt;Vth, this memory cell in the 1 state draws a drain current from the bit line so as to lower the potential of the bit line. On the other hand, the reference voltage Vref generated by a dummy cell set to the 0 state does not depend upon the read voltage Vgs. Accordingly, as is shown in FIG. 2, when Vgs&gt;Vth, the potential of the bit line lowered by the memory cell in the 1 state may be lower than the reference potential Vref, and in such a case, a read error occurs. A similar read error can occur when the threshold voltage of the memory cell in the 1 state is set to be lower than the maximum read voltage Vgsmax in order to solve the problem of the long time required for a program operation.